AVS 53rd International Symposium
    Plasma Science and Technology Monday Sessions

Session PS2-MoM
Advanced Gate Fabrication

Monday, November 13, 2006, 8:00 am, Room 2011
Moderator: E.V. Barnat, Sandia National Laboratories


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Click a paper to see the details. Presenters are shown in bold type.

8:00am PS2-MoM1
Plasma Etch Challenges in Non-Planar Device Fabrication
U. Shah, R.B. Turkot, Jr, T. Ghosh, S. Shankar, Intel Corporation
8:20am PS2-MoM2
Effect of Photoresist Trimming and Plasma Treatments on Line Roughness, Necking, and Bending During High Density Plasma Polysilicon Gate Etching
S.A. Vitale, B.A. Smith, J.W. Blatchford, B.M. Rathsack, Texas Instruments
8:40am PS2-MoM3
Understanding the Impact of Chamber Walls during Plasma Etching: a Key to Control Plasma Processes In ULSI
R. Ramos, Freescale Semiconductor, France, G. Cunge, O. Joubert, Laboratoire des Technologies de la Microelectronique, CNRS-LTM, France, M. Orlowski, Freescale Semiconductor, France, T. Lill, Applied Materials
9:00am PS2-MoM4
Effect of Etching Process on Gate LER
A. Yabata, O. Koike, J. Hashimoto, I. Kurachi, Miyagi Oki Electric Co., Ltd., Japan
9:20am PS2-MoM5
Plasma Atomic Layer Etching Using Conventional Plasma Equipment*
A. Agarwal, University of Illinois at Urbana-Champaign, M.J. Kushner, Iowa State University
9:40am PS2-MoM6
Impact of Plasma Damage on Cobalt Silicidation
T. Kimura, K. Kugimiya, K. Fuke, T. Ohchi, T. Kataoka, T. Tatsumi, Y. Kamide, Sony Corporation, Japan
10:20am PS2-MoM8 Invited Paper
Plasma Etching Challenges of New Materials Involved in Gate Stack Patterning for sub 45 nm Technological Nodes
O. Joubert, CNRS-LTM-France, A. Le Gouil, STM-France, R. Ramos, CNRS-LTM-France, M. Helot, STM-France, O. Luere, E. Richard, G. Cunge, T. Chevolleau, E. Pargon, L. Vallier, CNRS-LTM-France, T. Morel, S. Barnola, CEA-LETI-France, T. Lill, J.P. Holland, A. Patterson, AMAT-USA
11:00am PS2-MoM10
Ta and Mo-based Metal Etch for Advanced Gate Stacks
E. Luckowski, A. Martinez, S. Rauf, Freescale Semiconductor, Inc.
11:20am PS2-MoM11
Influence of Stopping Layer Nature on Poly-Si/Metal Gate Patterning Process
V. Paraschiv, D. Shamiryan, M. Demand, S. Beckx, IMEC, Belgium, C.G.N. Lee, G. Kota, LAM Research, W. Boullart, IMEC, Belgium
11:40am PS2-MoM12
Plasma Etching of Tungsten Nitride for sub 45nm Metal Gate
S. Barnola, CEA-LETI/France, T. Morel, STMicroelectronics