AVS 53rd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoM

Paper PS2-MoM1
Plasma Etch Challenges in Non-Planar Device Fabrication

Monday, November 13, 2006, 8:00 am, Room 2011

Session: Advanced Gate Fabrication
Presenter: U. Shah, Intel Corporation
Authors: U. Shah, Intel Corporation
R.B. Turkot, Jr, Intel Corporation
T. Ghosh, Intel Corporation
S. Shankar, Intel Corporation
Correspondent: Click to Email
As transistor development embraces multi-gate devices, new requirements are being placed on the patterning of these new structures. This paper discusses the challenges surrounding plasma etching of non-planar poly silicon gate electrodes required for multi-gate transistor development. The variation in type of structures, underlying materials and aspect ratios will be discussed. Some of the most common problems pertaining to etch processes of traditional planar devices such as gate profiles, notching, charge-induced damage of underlying material and selectivity requirements will be compared and contrasted between planar and non-planar geometries. Simulation results and models of how topography and underlying materials affects gate evolution and methods to control them will also be presented. Current metrology options used to characterize gate patterning and their inherent limitations will also be discussed in this paper.