AVS 53rd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoM

Paper PS2-MoM12
Plasma Etching of Tungsten Nitride for sub 45nm Metal Gate

Monday, November 13, 2006, 11:40 am, Room 2011

Session: Advanced Gate Fabrication
Presenter: S. Barnola, CEA-LETI/France
Authors: S. Barnola, CEA-LETI/France
T. Morel, STMicroelectronics
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With the reduction of the CMOS devices dimensions on standard poly-silicon gates, the poly depletion effect is a major problem to achieve low equivalent oxide thickness. Inserting a well chosen metal layer between the poly-silicon and the dielectric is one of the solutions, which transform a pure silicon gate into a metal gate where the work function of the metal layer is a key factor The use of thin MOCVD tungsten nitride layers (10nm) to achieve the PMOS devices on 300mm wafers is pretty novel. Its integration into a complete gate stack (Poly-Si/TiN/WN/SiO@sub 2@ or highK) is quite challenging in terms of dry etch. In this work we focused on understanding the etch mechanisms of tungsten nitride in chlorine and fluorine based chemistries on a 300mm ICP tool, with in-situ optical emission spectroscopy and in-situ interferometer. We investigated the selectivity over several dielectrics (SiO@sub 2@ and Hafnium based material) on blanket wafers. Chemical analysis of the interaction layers were performed by X-ray Photoelectron Spectroscopy (XPS) on the involved materials. High selectivity numbers (@>=@50:1) were easier obtained on Hafnium based dielectric than on SiO@sub 2@, especially in fluorine based chemistries with the low volatility of the hafnium by products. Nevertheless, good enough selectivity numbers were also achieved on SiO@sub 2@ in fluorine chemistry at low bias voltage. The integration of the WN etch into a multiple steps process for sub 45nm metal gates was investigated in terms of CD & profile control by Scanning Electron Microscopy (SEM).