AVS 53rd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoM

Paper PS2-MoM4
Effect of Etching Process on Gate LER

Monday, November 13, 2006, 9:00 am, Room 2011

Session: Advanced Gate Fabrication
Presenter: A. Yabata, Miyagi Oki Electric Co., Ltd., Japan
Authors: A. Yabata, Miyagi Oki Electric Co., Ltd., Japan
O. Koike, Miyagi Oki Electric Co., Ltd., Japan
J. Hashimoto, Miyagi Oki Electric Co., Ltd., Japan
I. Kurachi, Miyagi Oki Electric Co., Ltd., Japan
Correspondent: Click to Email
In nano-scaled regime of semiconductor devices, effect of gate process on MOSFET is getting large. Especially for etching performance, shrinking technique and stable uniformity length are strictly required. In addition to them, reduction in LER (Line Edge Roughness) is very important too. It is the most critical issue for variability of current status and off stage leakage. Therefore, LER must be reduced for improving MOSFET. In widely study, LER is well known being large in 193nm ArF lithography and has poor durability for etching plasma exposure. But effect of another process parameter is not enough understood yet. In this paper, we focused on gate etching process and gate electrode material,and found new mechanism of gate LER formation.@footnote 1@ LER was evaluated by 3D AFM(Atomic Force Microscope) with sample of PR/BARC/PolySi/Oxide/Si sub. 3D AFM is directly measurement system of sidewall roughness with flared type tip. Firstly, effect of PR/BARC LER on gate LER was evaluated. PR/BARC LER was controlled by changing BARC etching gas chemistry. From the result, gate LER did not change at all without effect of drastic PR/BARC LER change. That indicates gate electrode LER must not be influenced by LER of masking layer. Secondary, the parameter of PolySi gate etching condition was focused. Dependence of pressure, source power, bias power and stage temperature were evaluated. From the result, effective parameter was only bias power and Gate LER was improved with increasing of bias power. That indicates LER has closely related with etching sputtering effect. Finally, we focus on effect of gate electrode material itself. It was was evaluated by surface roughness of PolySi. It was controlled by phosphorus dope method,concentration and anneal condition. From the result, gate LER was closely related with surface roughness. Therefore, gate electrode material is a key factor of LER formation. @FootnoteText@ @footnote 1@A.Yabata,et.al.:ICRP-6/SPP-23(2006) P-2A-30 451.