AVS 53rd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoM

Invited Paper PS2-MoM8
Plasma Etching Challenges of New Materials Involved in Gate Stack Patterning for sub 45 nm Technological Nodes

Monday, November 13, 2006, 10:20 am, Room 2011

Session: Advanced Gate Fabrication
Presenter: O. Joubert, CNRS-LTM-France
Authors: O. Joubert, CNRS-LTM-France
A. Le Gouil, STM-France
R. Ramos, CNRS-LTM-France
M. Helot, STM-France
O. Luere, CNRS-LTM-France
E. Richard, CNRS-LTM-France
G. Cunge, CNRS-LTM-France
T. Chevolleau, CNRS-LTM-France
E. Pargon, CNRS-LTM-France
L. Vallier, CNRS-LTM-France
T. Morel, CEA-LETI-France
S. Barnola, CEA-LETI-France
T. Lill, AMAT-USA
J.P. Holland, AMAT-USA
A. Patterson, AMAT-USA
Correspondent: Click to Email
In plasma etching processes, the complexity comes from the introduction of new materials and from the reduction in dimension of the structures involved in CMOS devices. In the gate stack patterning step, the precision of the critical dimension (CD) control required to pattern silicon gates on thin SiON dielectrics has required an unprecedented effort of the etch community to design all the plasma etching steps allowing a CD control better than 3 nm across a 300 mm wafers. The introduction of metal layers and high K dielectric materials in the sub 45 nm gate stack is even more challenging since time and experience are missing to reach the degree of control required to fabricate such complex stacks in a range of dimension between 20-30 nm. In this presentation, we will show what new issues are faced when a metal layer is introduced in the gate stack: etch chemistry compatibility between silicon and metal (strongly metal dependent), profile deformation of the silicon top part of the gate when etching the thin metal layer, process strategy (etch silicon and metal in one step or in two steps), impact of chamber wall coatings on profile control and selectivity issues between metal and high K. The etching of high K HfO@sub 2@ based materials is also complex. First, after metal etching, the thin high K layer has been modified (covered by significant concentrations of halogens, roughness). Furthermore, the thin high K layer must be removed without generating damage in the underlying silicon and without generating profile deformation of the top part of the gate. All the issues will be discussed by showing the practical integration of TiN, TaN, WN, W in advanced gate stacks and discussing our results with the support of powerful in situ characterization techniques such as chemical topography analyses using XPS, mass spectrometry, as well as TEM and SEM cross sections.