AVS 49th International Symposium
    Plasma Science Thursday Sessions

Session PS-ThA
Dielectric Etch II

Thursday, November 7, 2002, 2:00 pm, Room C-103
Moderator: A.P. Mahorowala, IBM T. J. Watson Research Center


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Click a paper to see the details. Presenters are shown in bold type.

2:00pm PS-ThA1
Etching Reaction Mechanism of Organic Low-k Dielectric Employing High-Density Plasmas and Multi-Beams
M. Hori, H. Nagai, Nagoya University, Japan, M. Hiramatsu, Meijo University, Japan, T. Goto, Nagoya University, Japan
2:20pm PS-ThA2
Modeling Dual Inlaid Feature Construction
P.J. Stout, S. Rauf, T. Sparks, D. Zhang, P.L.G. Ventzek, Motorola
2:40pm PS-ThA3
Profile Evolution During Fluorocarbon Plasma Etching of Low-k Porous Silica@footnote 1@
A. Sankaran, M.J. Kushner, University of Illinois at Urbana-Champaign
3:00pm PS-ThA4
The Effect of Aspect Ratio on the Etching Properties of Porous Low-k Material in Fluorocarbon Plasma
S.H. Moon, S.-W. Hwang, G.-R. Lee, J.-H. Min, Seoul National University, Korea
3:20pm PS-ThA5
Etching of Porous Low-K Dielectric Films in Fluorocarbon Plasmas
S.A. Rasgon, B.E. Goodlin, H.H. Sawin, Massaschusetts Institute of Technology
3:40pm PS-ThA6
Plasma Etching Chemistry and Kinetics for Low-k and Porous Low-k Dielectric Films
W. Jin, Massachusetts Institute of Technology
4:00pm PS-ThA7
In Situ Real Time Monitoring of Evaporation Induced Self-Assembly and Patterned Etching of Low-k Mesoporous SiO@sub 2@ in Fluorocarbon Plasmas
H. Gerung, C.J. Brinker, S. Han, University of New Mexico
4:20pm PS-ThA8
The Control of the Etching of SiOCH Films using C@sub 4@F@sub 8@/Ar/N@sub 2@ Plasma
T. Tatsumi, Sony Corporation, Japan, K. Urata, Sony Computer Entertainment, Japan, K. Nagahata, Sony Corporation, Japan, S. Iseda, Sony Computer Entertainment, Japan, Y. Morita, Sony Corporation, Japan
4:40pm PS-ThA9
SiO@sub 2@ Etch Lag in SiO@sub 2@/SiLK@super TM@/SiO@sub 2@ Stack Structures
A. Hasegawa, K. Ohira, T. Mizutani, Fujitsu Limited, Japan, K. Higuchi, Fujitsu Vlsi Limited, Japan, M. Okamoto, M. Nakaishi, K. Nakagawa, Fujitsu Limited, Japan
5:00pm PS-ThA10
Etch Process Development of Porous Low-k Dielectrics for Dual Damascene Copper Interconnects
K.D. Brennan, Texas Instruments, J.M. Jacobs, Philips, P.J. Wolf, Intel