AVS 49th International Symposium
    Plasma Science Thursday Sessions
       Session PS-ThA

Paper PS-ThA9
SiO@sub 2@ Etch Lag in SiO@sub 2@/SiLK@super TM@/SiO@sub 2@ Stack Structures

Thursday, November 7, 2002, 4:40 pm, Room C-103

Session: Dielectric Etch II
Presenter: A. Hasegawa, Fujitsu Limited, Japan
Authors: A. Hasegawa, Fujitsu Limited, Japan
K. Ohira, Fujitsu Limited, Japan
T. Mizutani, Fujitsu Limited, Japan
K. Higuchi, Fujitsu Vlsi Limited, Japan
M. Okamoto, Fujitsu Limited, Japan
M. Nakaishi, Fujitsu Limited, Japan
K. Nakagawa, Fujitsu Limited, Japan
Correspondent: Click to Email
The etching of stack structure using hard-mask became indispensability by the adoption of the dual damascene process and organic low dielectric constant (k) material for Cu wiring. In this study, SiO@sub 2@ etch lag effect depending on existence of SiLK@super TM@ layer in stack structure is investigated. SiLK@super TM@ is low-k organic dielectrics considered as perspective candidates for the use in microelectronic industry. The sample used in this experiment consists of SiN/upper SiO@sub 2@/SiLK@super TM@/lower SiO@sub 2@ stacked structure. SiN was used for hard-mask to etch SiO@sub 2@. Upper SiO@sub 2@ was used for cover layer to protect SiLK@super TM@ damage during ashing and/or planarization by chemical mechanical polishing. After SiN trench etch, SiN/upper SiO@sub 2@/SiLK@super TM@ were etched using hole patterned photoresist mask. Photoresist mask was removed during SiLK@super TM@ etch. Then, trench pattern of upper SiO@sub 2@ and via pattern of lower SiO@sub 2@ were etched at the same time using the patterned SiN/upper SiO@sub 2@/SiLK@super TM@ layers. The etching of the upper and lower SiO@sub 2@ were performed in commercial UHF plasma reactors using a C@sub 5@F@sub 8@/Ar/O@sub 2@ chemistry. The lower SiO@sub 2@ etch depth was measured from cross-sectional-scanning-electron-microscopy (SEM) photographs. The etch rate of dense via was 284nm/min. On the other hand, in the isolated via, the etch rate was only 91nm/min. However, in the case of using the stack sample, which was replaced SiLK@super TM@ with SiN, etch rate of dense and isolated via were equivalent at 282nm/min. It was found that existence of SiLK@super TM@ decreases the SiO@sub 2@ etch rate of a particular via pattern remarkably.