AVS 49th International Symposium
    Plasma Science Thursday Sessions
       Session PS-ThA

Paper PS-ThA10
Etch Process Development of Porous Low-k Dielectrics for Dual Damascene Copper Interconnects

Thursday, November 7, 2002, 5:00 pm, Room C-103

Session: Dielectric Etch II
Presenter: K.D. Brennan, Texas Instruments
Authors: K.D. Brennan, Texas Instruments
J.M. Jacobs, Philips
P.J. Wolf, Intel
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Advances in plasma etch technology are necessary to integrate low-k dielectrics and low-resistance metal leads to reduce interconnect RC time delay in order to meet the requirements of the International Technology Roadmap for Semiconductors (ITRS). International SEMATECH (ISMT) is currently implementing dual damascene copper interconnects built with porous low-k dielectrics as a means to meet future interconnect requirements. Development and optimization of an etch process for JSR LKD 5109, a porous methyl-silsesquioxane (pMSQ) based dielectric with a k-value of 2.2 is presented. Two level metal interconnects are fabricated, using a dual hard mask approach. The advantages and limitations of this approach for the etch process are discussed.