AVS 51st International Symposium
    Plasma Science and Technology Tuesday Sessions

Session PS2-TuM
New Gate Conductor Etching

Tuesday, November 16, 2004, 8:20 am, Room 213B
Moderator: C. Labelle, Advanced Micro Devices


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  in Adobe Acrobat format  

Click a paper to see the details. Presenters are shown in bold type.

8:20am PS2-TuM1
Study of Refractory Metal Nitrides/HfO@sub 2@ Gate Stack Etching Using Inductively Coupled Plasma
J.H. Chen, W.S. Hwang, W.J. Yoo, S.H.D. Chan, National University of Singapore, Singapore, D.-L. Kwong, University of Texas, Austin
8:40am PS2-TuM2
Line Width Roughness Reduction for Advanced Metal Gate Etch and STI Etch with 193nm Lithography in a Silicon Decoupled Plasma Source Etcher (DPSII)
T. Chowdhury, H. Lee, A. Renaldo, K. Ikeuchi, A. Habbermas, B. Bruggermann, Cypress Semiconductor, Y. Du, M. Shen, S. Deshmukh, J. Choi, Applied Materials, Inc.
9:00am PS2-TuM3
Plasma Etching of Metal/High-K Gate Stack
A. Le Gouil, STMicroelectronics, France, T. Chevolleau, G. Cunge, L. Vallier, O. Joubert, LTM-CNRS, France, P. Mangiagalli, T. Lill, Applied Materials
9:20am PS2-TuM4
Etching Ruthenium with O2- and Cl2-Containing Inductively Coupled Plasma
C.-C. Hsu, D.B. Graves, J.W. Coburn, University of California, Berkeley
9:40am PS2-TuM5
Ru Etching Characteristics in Capacitively Coupled Ar/Cl@sub 2@/O@sub 2@ Plasma
S. Rauf, P.L.G. Ventzek, V. Vartanian, B. Goolsby, Freescale Semiconductor, S. Burnett, International Sematech, L. Chen, Tokyo Electron America Inc.
10:00am PS2-TuM6
An Isotropic SiGe Etch Process for Fabrication of Silicon-on-Nothing Transistors
T. Sparks, S. Rauf, Freescale Semiconductor, France, G. Cunge, L. Vallier, LTM-CNRS, France
10:20am PS2-TuM7
X-ray Photoelectron Spectroscopy Study on Walls Coatings and Passivation Layers Generated on Sidewalls Trenches during Shallow Trench Isolation Processes.
C. Maurice, B. Pelissier, G. Cunge, O. Joubert, LTM-CNRS, France
10:40am PS2-TuM8
The Control of Electrode Impedance, Gas-Injection and Wafer-Temperature Radial Profile and their Effects on Poly-Gate Etching Performance
M.H. Hagihara, L.C. Chen, F.H. Higuchi, Y.T. Tsukamoto, K.I. Inazawa, TEL, T.T. Tatsumi, A.K. Kawashima, Sony
11:00am PS2-TuM9
Process Diagnostics and Optimization in Plasma Etch Chambers Using In-Situ Temperature Metrology
P. MacDonald, OnWafer Technologies, Inc., B. Hatcher, J.P. Holland, Applied Materials, Inc., M. Welch, M. Kruger, OnWafer Technologies, Inc.
11:20am PS2-TuM10
New Mthod to Analyse Chamber Walls Coating during Plasma Etch Processes
O. Joubert, G. Cunge, B. Pelissier, C. Maurice, L. Vallier, LTM-CNRS, France