AVS 51st International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Paper PS2-TuM10
New Mthod to Analyse Chamber Walls Coating during Plasma Etch Processes

Tuesday, November 16, 2004, 11:20 am, Room 213B

Session: New Gate Conductor Etching
Presenter: O. Joubert, LTM-CNRS, France
Authors: O. Joubert, LTM-CNRS, France
G. Cunge, LTM-CNRS, France
B. Pelissier, LTM-CNRS, France
C. Maurice, LTM-CNRS, France
L. Vallier, LTM-CNRS, France
Correspondent: Click to Email
In today's etching processes for microelectronic application the shape of the etched feature must be controlled within 5 nm. This nanometer-scale linewidth control requires a perfect process repeatability. In high density plasmas operating at low pressure it is difficult to achieve due to the deposition of organic (or mineral) layers on the reactors walls during the process. This formation of this layer on the reactor walls modifies the surface loss probability and the concentrations of radicals involved in the etching process, leading to process instabilities. However, the chemical nature of these layers, their deposition mechanism and their influence on the plasma chemistry remains poorly understood. Recently, we have developed a new and very simple method based on the fact that a small piece of Al@sub 2@O@sub 3@ floating on top of a 200 mm diameter wafer during an etch process experiences the same exposition to the plasma than the chamber walls. We have then use quasi in situ XPS measurements to have access to the chemical nature of the layers formed on the floating Al@sub 2@O@sub 3@, i.e the chamber walls, during plasma etching processes. Using this technique, we can determine accurately the chemical nature of the layers coated on the reactor walls after various etching processes including silicon and metal (TiN) gate etching. We will demonstrate that the final nature of the chamber wall coatings is strongly influenced by the presence of resist on the wafer, nature of the layers composing the gate stack and chemistries used during the different steps of the process. We will then discuss the cleaning strategies that are commonly used after gate etching processes and their limitations.