AVS 51st International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Paper PS2-TuM3
Plasma Etching of Metal/High-K Gate Stack

Tuesday, November 16, 2004, 9:00 am, Room 213B

Session: New Gate Conductor Etching
Presenter: A. Le Gouil, STMicroelectronics, France
Authors: A. Le Gouil, STMicroelectronics, France
T. Chevolleau, LTM-CNRS, France
G. Cunge, LTM-CNRS, France
L. Vallier, LTM-CNRS, France
O. Joubert, LTM-CNRS, France
P. Mangiagalli, Applied Materials
T. Lill, Applied Materials
Correspondent: Click to Email
The rapid downscaling of metal-oxide-semiconductor transistors imposes new materials for the gate stack. Metal gate electrode receives more attention than conventional poly-Si gate electrode when high permittivity material is used as the gate dielectric. In addition to the introduction of these new materials, critical dimension control of less than 3nm must be achieved for the 45 nm technological node. In this work the metal gate etching process is developed with a poly-Si/TiN stack for the gate electrode and HfO@sub2@ (3.5 nm thick) as the gate dielectric. Anisotropic and selective etching of the gate stack requires the development of a multi-step etching process. First, the silicon part of the gate is etched using an HBr/Cl@sub2@/HeO@sub2@-based chemistry. We have then studied several chemistries (Cl@sub2@ , HBr and their mixture) to etch the TiN layer anisotropically and selectively with respect to HfO@sub2@. The selectivity and surface modification of the HfO@sub2@ layer after exposition to the plasmas have been studied by X-ray Photoelectron Spectroscopy and AFM. While highly anisotropic etching can be observed in pure Cl@sub2@ plasmas, a very rough HfO@sub2@ surface is observed in this case, partially due to the presence of TiO@subx@ residues on the HfO@sub2@ surface. In addition the selectivity toward HfO@sub2@ is poor. By contrast HBr provides a higher selectivity with less roughness. Hence using a mixture of HBr/Cl@sub2@ appears to be the best strategy to achieve both anisotropic and selective etching of TiN film over HfO@sub2@. Finally, a complete metal gate process requires HfO@sub2@ removal after the gate definition. We will show that this high temperature plasma process can seriously damage the gate profile due to the lack of passivation layer on the TiN sidewalls (undercutting is observed). This suggests that a protection layer must be formed after or during TiN etching in order to protect the metal gate before removal of the dielectric of the gate.