AVS 51st International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS2-TuM

Paper PS2-TuM2
Line Width Roughness Reduction for Advanced Metal Gate Etch and STI Etch with 193nm Lithography in a Silicon Decoupled Plasma Source Etcher (DPSII)

Tuesday, November 16, 2004, 8:40 am, Room 213B

Session: New Gate Conductor Etching
Presenter: T. Chowdhury, Cypress Semiconductor
Authors: T. Chowdhury, Cypress Semiconductor
H. Lee, Cypress Semiconductor
A. Renaldo, Cypress Semiconductor
K. Ikeuchi, Cypress Semiconductor
A. Habbermas, Cypress Semiconductor
B. Bruggermann, Cypress Semiconductor
Y. Du, Applied Materials, Inc.
M. Shen, Applied Materials, Inc.
S. Deshmukh, Applied Materials, Inc.
J. Choi, Applied Materials, Inc.
Correspondent: Click to Email
193nm lithography has become necessary as the critical dimensions of semiconductor devices continue to scale down towards sub 90 nm dimension. From a device point of view the effects of higher Line Edge Roughness (LER)/Line Width Roughness (LWR) are studied. Metrology aspects of LER/LWR are also included in the study. From dry etching perspective, however, 193nm resist brings new challenges due to its poorer plasma etch resistance, LER/LWR and lower thickness compared to 248nm DUV resist. This paper presents a successful development of advanced 0.1µm metal gate and STI etch application using 193nm lithography on Applied Materials' decoupled plasma etcher DPSII system. Process chemistry and process parameters for nitride mask step were thoroughly explored and investigated vs LWR. Post-etch measurement of line width roughness shows an average of 6nm LWR. It was observed LWR is a strong function of etch chemistry (CHF3/CF4 based HM open vs CH2F2 based HM Open), reaction regime (15 mT vs 30 mT) and ICP vs MERIE etc. A detailed study showing methods to reduce LWR is presented in this paper. .