AVS 47th International Symposium
    Plasma Science and Technology Monday Sessions

Session PS2-MoA
Plasma Etching of Conductors

Monday, October 2, 2000, 2:00 pm, Room 311
Moderator: A. Kornblit, Bell Laboratories, Lucent Technologies


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  in Adobe Acrobat format  

Click a paper to see the details. Presenters are shown in bold type.

2:00pm PS2-MoA1
Gate Engineering for sub 50 nm CMOS Devices
J. Foucher, CNRS/LTM, France, G. Cunge, CEA/LETI, France, D. Fuard, R.L. Inglebert, L. Vallier, O. Joubert, CNRS/LTM, France
2:20pm PS2-MoA2
Fabrication of 80 nm PN-poly/metal Gate on Ultra-thin 1.5 nm Oxynitride
K. Kinoshita, S. Saito, Y. Saito, M. Narihiro, M. Ueki, H. Wakabayashi, Y. Ochiai, T. Mogami, Y. Hayashi, NEC Corporation, Japan
2:40pm PS2-MoA3
Etch Rate Enhancement and Surface Roughening during W/Poly Si Stack Gate Etching Process
H. Morioka, M. Nakaishi, T. Ishida, Fujitsu Limited, Japan
3:00pm PS2-MoA4
A Drift of Selectivity Depending on Chamber Seasonings in a Poly-Si/Oxide Etching Process using Inductively Coupled Plasma
K. Miwa, Fujitsu VLSI Ltd., Japan, T. Mukai, M. Nakaishi, Fujitsu Ltd., Japan
3:20pm PS2-MoA5
Novel Dry Etch Chemistries for Metals
A. Orland, R. Blumenthal, Auburn University
3:40pm PS2-MoA6
Experimental and Modeling Results for Process Scaling from 200 mm to 300 mm Wafers
S.C. Siu, D. Cooperberg, V. Vahedi, R. Patrick, Lam Research Corporation
4:00pm PS2-MoA7
Improving Al Etch Processing in a High Density Plasma Reactor with a Faraday Shield
D.A. Outka, S.C. Siu, N. Williams, Lam Research Corp.
4:20pm PS2-MoA8
Transfer Etch Profile Control for 248 nm Bilayer Thin Film Imaging
S. Halle, R. Wise, J. Brown, IBM Microelectronics, O. Genz, Infineon Technologies Corporation, A. Thomas, T. Dyer, IBM Microelectronics, A.P. Mahorowala, M. Angelopoulos, IBM T.J. Watson Research Center, S. Johnston, Lam Research Corporation
4:40pm PS2-MoA9 Invited Paper
Conductor Stack Etching: Technology and Productivity
R.A. Gottscho, Lam Research Corporation