Conductor etching in the semiconductor industry includes front-end applications such as gate and shallow trench stacks as well as back-end interconnect structures. Future applications center around new materials for gate stacks, to accomodate decreasing voltages and dielectric thickness, and high-k dielectrics, to enable higher density and powerless storage. The technological requirements in gate stack etching center on within wafer critical dimension, CD, control; but, production considerations demand equal attention to wafer-to-wafer, lot-to-lot, and machine-to-machine CD uniformity. For within wafer CD uniformity, gas injection, pumping, plasma generation, and edge ring design all play important roles. However, the aspect ratio variations inherent in circuit design and doping variations within the stack or from stack-to-stack ultimately limit the process window. Waferless cleaning of the chamber and delivered power control provide effective means for minimizing CD variation during large volume production. To preserve the device integrity of ultra-thin gate oxides and maximize yield, novel pre-end-point detection is used with and highly selective over-etch processes. Shallow trench etching mechanisms appear identical to those governing gate stack etching, but by shifting the balance between etching and deposition, trench profiles can be tailored to meet demanding requirements for top rounding, bottom rounding, and side-wall-angle uniformity. In back-end etching, traditional trade-offs remain for resist mask stacks: vertical profiles without residues and charging damage. Hard mask metal etching offers wider process window but at higher cost. The primary focus in the back-end is output, to be gained by increased throughput and longer times between cleans. It is the latter that is driving innovative changes in reactor designs and materials.