AVS 47th International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoA

Paper PS2-MoA1
Gate Engineering for sub 50 nm CMOS Devices

Monday, October 2, 2000, 2:00 pm, Room 311

Session: Plasma Etching of Conductors
Presenter: J. Foucher, CNRS/LTM, France
Authors: J. Foucher, CNRS/LTM, France
G. Cunge, CEA/LETI, France
D. Fuard, CNRS/LTM, France
R.L. Inglebert, CNRS/LTM, France
L. Vallier, CNRS/LTM, France
O. Joubert, CNRS/LTM, France
Correspondent: Click to Email
In less than ten years, we will be approaching the limits of the CMOS technology with typical gate transistor length of less than 30 nm. In the past, gate etch processes have been optimised to provide perfectly straight sidewalls while maintaining the selectivity to the ultra-thin gate oxide (less than 2 nm). Recently, a new approach has been proposed in which the process is tuned to obtain a silicon-based gate whose dimension is smaller at the bottom than at the top of the gate (notched gate). This new approach opens up the possibility of making gates with dimensions smaller than the ultimate resolution of the lithography. In this paper we discuss the mechanisms involved in the fabrication of notched gate. Experiments have been conducted on a very powerful plasma etch system dedicated to advanced studies. It consists in a Decoupled Plasma Source (DPS) from Applied Materials modified to host in situ diagnostics such as UV-visible ellipsometry, mass spectrometry, fast injection Langmuir probe and X-ray photoelectron spectroscopy (XPS). Oxide masked a-si gates are etched using a modified etch recipe allowing a lateral erosion of silicon to be obtained at bottom of the gate. This can be achieved by tuning the thickness and composition of the passivation layer formed on the silicon sidewalls (sidewall passivation layer engineering). The robustness of the sidewall passivation layer is reinforced in the first part of the process while, on the other hand, plasma conditions are tuned in the second part of the process to suppress the passivation layer. In a last step, lateral erosion of the silicon sidewall is possible at the location where no passivation layer has been formed. XPS data of the passivation layer formed at the different process steps will be shown as well as some details on the control of the notch depth. Finally some results showing gate dimension in the 20 nm range will be shown.