AVS 53rd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS-MoA

Invited Paper PS-MoA3
Patterning Technology for Sub-50 nm Memory Devices

Monday, November 13, 2006, 2:40 pm, Room 2009

Session: Manufacturing and Scientific Challenges for Plasma Processing at 32 nm
Presenter: C.-J. Kang, SAMSUNG Electronics, Korea
Correspondent: Click to Email
In the era of sub-50 nm memory devices, patterning technology encounters many challenges, which arise from the introduction of immersion ArF lithography with high numerical aperture, a complex device structure, and the use of new materials. First of all, in the immersion technology, 100 nm thickness of ultra-thin resist process is used and it is likely to generate particles to cause defects. In addition, the reduction of a line width roughness (LWR) and overlay error between layers are getting more difficult. Second, in the plasma etching technology, the advanced features such as 3 dimensional FinFET structure force to develop a highly selective etching process. Finally, the introduction of new materials such as High-k dielectric, metal gate, and phase change materials are more challenging in the view point of profile and selectivity. Since the process window is getting narrow, control and monitoring technologies such as advanced process control (APC) and advanced equipment control (AEC) are strongly required. For the development and manufacturing of sub 50-nm memory devices, the patterning technologies should overcome many difficulties, which is related to not only the lithography and etching process itself, but also hardware development.