AVS 52nd International Symposium
    Plasma Science and Technology Wednesday Sessions
       Session PS-WeM

Paper PS-WeM9
Damage-free MOS Gate Electrode Patterning on Thin HfSiON Film Using a Neutral Beam Etching

Wednesday, November 2, 2005, 11:00 am, Room 304

Session: Advanced Gate Stack Fabrication
Presenter: S. Noda, Tohoku University, Japan
Authors: S. Noda, Tohoku University, Japan
T. Ozaki, Tohoku University, Japan
S. Samukawa, Tohoku University, Japan
Correspondent: Click to Email
We have already reported that our newly developed neutral beam could realize highly anisotropic gate electrode patterning on thin SiO@sub 2@ film with reasonable etching rate and etching selectivity.@footnote 1@ In this paper, radiation damages during the gate electrode patterning on thin HfSiON gate dielectric films (2nm) were investigated in our system. By changing the beam acceleration method (DC or RF voltages) in the neutral beam source, the beam flux and its composition (ratio between neutral and charged particles) could be controlled on the surface. Then, the leakage current of gate dielectric film was measured with antenna MOS capacitors. Although the gate leakage currents of the MOS capacitors measured just after the etching of poly-Si electrodes slightly increased in any conditions, its values were sufficiently lower (less than 1/10) than that in a conventional plasma etching. Since the leakage current increased according to over etching time, it was understood that a little degradation was caused by small stress current through the thin gate dielectric films due to the residual charges even during the neutral beam etching process. However, the residual charge current was extremely low and degradation of the gate dielectrics was negligibly small even if annealing was not performed in the neutral beam process. @FootnoteText@ @footnote 1@S. Noda et al., JVST A22,1506 (2004).