AVS 52nd International Symposium
    Plasma Science and Technology Wednesday Sessions
       Session PS-WeM

Paper PS-WeM5
Challenges in Plasma Etching of Metal Gate Stacks

Wednesday, November 2, 2005, 9:40 am, Room 304

Session: Advanced Gate Stack Fabrication
Presenter: A. Le Gouil, STMICROELECTRONICS
Authors: A. Le Gouil, STMICROELECTRONICS
E. Richard, LTM (CNRS), France
T. Chevolleau, LTM (CNRS), France
G. Cunge, LTM (CNRS), France
O. Joubert, LTM (CNRS), France
L. Vallier, LTM (CNRS), France
Correspondent: Click to Email
The rapid downscaling of metal-oxide-semiconductor transistors imposes the introduction of metal gates electrodes and high k gate dielectrics. Hence the patterning of a typical gate stack (Si/metal/high-k) requires the development of new etching processes. In this work the metal gate etching process is developed with both poly-Si/TiN and poly-Si/TaN stack for the gate electrode and HfO@sub2@ or HfSiO (3.5 nm thick) as the gate dielectric. First, the silicon part of the gate is etched using a standard HBr/Cl@sub2@ silicon gate etching process, which is followed by the metal etching step. By comparison with classical silicon etch processes two main issues are identified during the etching of the metal gate stack. First, when silicon etching stops on a metal instead of a SiO@sub2@ layer, a slope is observed at the bottom of the silicon etch profile. This difference is attributed to charging effect: charge accumulation on the insulator gate oxide deviate the ions towards the bottom of the gate (thus eliminating the gate foot), while this does not occur on a conductive metallic layer. Second, in the HBr-rich chemistry that is needed to etch the metal layer selectively towards the gate dielectric, a strong slope is systematically observed in the metal etch profile. This slope is attributed to the continuous increase of the mask dimension during the etching process due to the redeposition of precursors on the mask and feature sidewalls. We will show that these precursors originates from the SiOCl coating formed on the reactor walls during the silicon etching process, and which is subsequently sputtered during the metal etching step. This is a serious issue for critical dimension control in metal gate etching processes, and potential strategies to minimize it will be investigated.