AVS 52nd International Symposium
    Plasma Science and Technology Wednesday Sessions
       Session PS-WeM

Invited Paper PS-WeM3
Challenges in Plasma Processing for Advanced Gate Stack Fabrication

Wednesday, November 2, 2005, 9:00 am, Room 304

Session: Advanced Gate Stack Fabrication
Presenter: B.-W. Chan, Taiwan Semiconductor Manufacturing Corp.
Authors: B.-W. Chan, Taiwan Semiconductor Manufacturing Corp.
Y.-H. Chiu, Taiwan Semiconductor Manufacturing Corp.
E. Luckowski, Freescale Semiconductor
B. Goolsby, Freescale Semiconductor
S. Rauf, Freescale Semiconductor
P.J. Stout, Freescale Semiconductor
B. White, Freescale Semiconductor
P. Tobin, Freescale Semiconductor
H.-J. Tao, Taiwan Semiconductor Manufacturing Corp.
S.-M. Jang, Taiwan Semiconductor Manufacturing Corp.
M.-S. Liang, Taiwan Semiconductor Manufacturing Corp.
Correspondent: Click to Email
High gate leakage current limits gate oxide thickness shrinkage in traditional SiO2 dielectrics. New gate stacks with novel material combinations are being investigated to reduce gate leakage while enhancing transistor performance. The combination of high K dielectrics and metal gates is a leading candidate for advanced CMOS gate materials but at the cost of increased complexity and greater challenge for the plasma processes that would be used to etch them. In this presentation, we will point out critical issues related to high K and metal gate etch and in particular dual metal gate fabrication. Examples of how simulation is being used to aid advanced gate etch development will also be presented. A specific focus of the talk will be gate trim process and resultant accurate critical dimension (CD) control and meeting CD control metrics required for beyond 65nm transistor fabrication.