AVS 52nd International Symposium
    Plasma Science and Technology Wednesday Sessions
       Session PS-WeM

Paper PS-WeM2
Ta Based Metal Gate Etch for Dual Metal Gate CMOS Applications

Wednesday, November 2, 2005, 8:40 am, Room 304

Session: Advanced Gate Stack Fabrication
Presenter: C.H. Huffman, Texas Instruments Assignee to SEMATECH
Authors: C.H. Huffman, Texas Instruments Assignee to SEMATECH
Z. Zhang, Texas Instruments Assignee to SEMATECH
S.C. Song, SEMATECH
Correspondent: Click to Email
Although the ITRS states that low power applications may require high-k materials first, the high performance devices trend will soon require both high-k dielectrics and metal gate electrodes to remove polysilicon depletion effects. The selection of the metal gate material will be driven by the workfunction of the metal in order to control the threshold voltage of the transistors. Candidate metals should have a workfunction within 0.1v of the conduction band and the valance band edges for NMOS and PMOS respectively. The potential NMOS candidate metals are more reactive while the PMOS candidates are more noble like and this creates an etch challenge for dual metal CMOS integration. This paper will discuss the formation of dual metal gate CMOS structures using Ta based metal electrodes (TaN, TaSiN, TaCN). Affects of plasma parameters on the various metals will be discussed with respect to successful construction of dual metal gate CMOS. Differences in recipes for the various metals will be compared and contrasted with respect to successful construction of advanced metal gate electrodes. Included in the discussion will be potential process solutions for some of the common multiple material gate etch issues that occur. Optical endpoint control will be included for selected materials and process steps.