The continuation of highly scaled Planar Bulk CMOS has been identified @footnote1@ as very difficult, if not impossible, at or beyond the 45nm Node due to short channel effects (SCE) and other parasitic effects. Several device structure options for "non-classical" CMOS have been proposed and fabricated in research environments, e.g., Ultra-Thin Body SOI (UTB-SOI) or Multiple-Gate FET (MuGFET) both using lightly doped bodies for scaling gate length Lg well below 20nm. Although these devices offer good device characteristics and scaling opportunities, fabrication and optimization of these devices for device level CMOS integration and production present inherently difficult challenges. This talk will identify and discuss many of these integration roadblocks and manufacturing challenges and discuss possible paths to overcome them. @FootnoteText@ @footnote 1@ International Technology Roadmap for Semiconductors 2003 Edition.