AVS 51st International Symposium
    Manufacturing Science and Technology Wednesday Sessions
       Session MS-WeM

Invited Paper MS-WeM1
Integration Challenges for 45nm Strained Si Devices

Wednesday, November 17, 2004, 8:20 am, Room 303B

Session: Semiconductor Manufacturing Technologies for the 45nm Crisis
Presenter: M. Sadaka, Freescale Semiconductor
Authors: M. Sadaka, Freescale Semiconductor
A. Thean, Freescale Semiconductor
A. Barr, Freescale Semiconductor
T. White, Freescale Semiconductor
B. Nguyen, Freescale Semiconductor
V. Vartanian, Freescale Semiconductor
M. Zavala, Freescale Semiconductor
D. Eades, Freescale Semiconductor
S. Zollner, Freescale Semiconductor
Q. Xie, Freescale Semiconductor
X. Wang, Freescale Semiconductor
R. Liu, Freescale Semiconductor
M. Kottke, Freescale Semiconductor
Correspondent: Click to Email
As power supply voltage becomes lower with successive scaling, the non-scalability of threshold-voltage and conventional gate oxide to maintain low stand-by leakage is rapidly reducing the maximum gate overdrive factor. Enhancing carrier mobility by biaxially-straining Si on relaxed SiGe on SOI and on Bulk substrates provides a viable option to sustain the continual drive current increase. Though strained-Si addition to conventional MOSFET seems minimally disruptive, the use of SiGe in CMOS devices introduces new process and device challenges, wafer quality requirements, substrate cost issues, and new metrology requirements for strain monitoring. All these challenges need to be addressed in order to prove successful manufacturability. This talk will focus on the integration challenges of strained Si devices. The process and device challenges include Ge up-diffusion into strained Si channel, dopant diffusion differences between Si and SiGe, NiSi versus CoSi, and the need for raised source drains (formed by selective epitaxy) due to Ge segregation with cobalt silicidation. Wafer quality requirements include reducing the defect density less than 10@super 3@ defects/cm@super 2@ in order to realize yielding, high density large circuits, while maintaining maximum levels of achievable strain at a reduced wafer cost relative to the cost of SOI wafers. Finally, the appropriate metrology specific to strained Si monitoring will be discussed.