The transition from Al metallization to Cu has been implemented during the past several years and successfully introduced into several device products. This has resulted in improvement in device chip speed due to the resistivity reduction. To further decrease the RC time delay and minimize cross talk between interconnect lines, the transition to low-k materials has been actively investigated but the implementation has not been as rapid or straightforward. The convergence of Cu metallization with low-k dielectric has been hampered by the difficulty in replacing the present SiO@sub2@ with a low-k material that meets all the film property requirements: mechanical, thermal and electrical compatibility. Key integration issues for the low-k material include dual damascene pattern definition, adhesion of the barrier/ seed and adequate planarization. A review of the various materials and technologies (PVD, CVD) to deposit the barrier/ seed will be presented along with the pre-clean methods to ensure low via resistance. A survey of the different barrier films and barrier testing will illustrate the need for evaluating not only out-diffusion of Cu into the dielectric but also the in-diffusion of other components from the dielectric (e.g. diffusion of F from FSG to Cu). The currently used Ta-based barriers will be compared with composite layered structures and new materials. The necessity for decreasing the seed layer thickness for electroplating fill has placed a greater demand on the step coverage and resultant interface properties. Recent advances in electroplating technology may resolve this issue and its impact on integration with low-k materials will be highlighted. These challenges will be further amplified with the introduction of porous low-k materials and may force the implementation of other technologies to satisfy the requirements for sub- 0.1 µm devices.