AVS 45th International Symposium
    Plasma Science and Technology Division Wednesday Sessions
       Session PS-WeA

Paper PS-WeA7
Investigation of Si-poly Etch Process for 0.1 µm Gate Patterning and Beyond

Wednesday, November 4, 1998, 4:00 pm, Room 318/319/320

Session: Plasma-Surface Interactions I
Presenter: L. Vallier, France Telecom-CNET
Authors: L. Vallier, France Telecom-CNET
L. Desvoivres, France Telecom-CNET
M. Bonvalot, France Telecom-CNET
O. Joubert, France Telecom-CNET
S. Tedesco, CEA-LETI, France
B. Dal’Zotto, CEA-LETI, France
Correspondent: Click to Email
The etching of dense and isolated 0.1µm gate structures has been studied in a high density plasma helicon source capable of processing 200 mm diameter wafers. The gate stack consists of 150 nm thick amorphous silicon film on a 2 nm thick gate oxide, covered with 50 nm thick SiO@sub 2@ patterns obtained using e-beam direct writing. HBr/O@sub 2@ gas chemistry is used for the etching; a 2 steps etching recipe using 2 RF bias regimes was developped in order to obtain anisotropic etching profiles without any etching anomalie(trenching, bowing, notching) while keeping a high selectivity on the very thin gate oxide. Real time ellipsometry was used either to measure etching rates or to monitor the arrival on the thin gate oxide. XPS analysis of the etched wafer is performed in an ultra high vacuum chamber after transfer under vacuum ; XPS data were obtained on dedicated structures with different aspect ratio allowing the gate oxide comsumption as well as sidewall passivation thickness to be precisely measured in dense areas. Attempts to measure CD variation due to the etch process and profiles anomalies related to the etching parameters will also be presented. @FootnoteText@ This work has been carried out within the GRESSI Consortium between CEA-LETI and France Telecom-CNET