| AVS 64th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS-WeM |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | Jeffrey Shearer, IBM Research Division |
| Authors: | J.C. Shearer, IBM Research Division A. Raley, TEL Technology Center, America, LLC A. De Silva, IBM Research Division L. Meli, IBM Research Division I.P. Seshadri, IBM Research Division R.K. Bonam, IBM Research Division N.A. Saulnier, IBM Research Division B. Briggs, IBM Research Division T. Oh, Samsung Electronics Co. Ltd. A. Metz, TEL Technology Center, America, LLC J.C. Arnold, IBM Research Division |
| Correspondent: | Click to Email |
The rising cost of implementing EUV lithography is often cited as a major detractor for its adoption in future semiconductor technology nodes. The ability to directly print EUV levels with a single exposure not only alleviates some of the cost of processing but also many of the process challenges associated with multiple patterning techniques. However, scaling EUV technology, notably beyond 36nm pitch, comes with its own challenges. For example, constraints on resist thickness and hardmask material choices have emerged as unique etch challenges for BEOL patterning. Both new etch chemistries and novel etch techniques, such as the implementation of quasi-atomic layer etching and DC superposition, have proven invaluable in patterning beyond 36nm pitch.
We have demonstrated capability for EUV single exposure patterning beyond 36nm pitch using both trilayer and quadlayer patterning stacks. This paper will highlight benefits and challenges of each in terms of etch development. Specifically, SiARC-based patterning stacks will be compared to organic BARC-based quadlayer stacks with various hard layers in them. The introduction of each stack material was tested at 36nm pitch before transferring to sub-36nm pitch devices. Each pitch and stack has its own set of etch considerations, and we will address their impact on pattern transfer capability, CD process window, LER/LWR, the effort and methods necessary to overcome resist scumming, line end pullback, and others. An analysis of etch parameter selection will show how defectivity can be improved for each material stack. A programmed roughness structure allows detailed LER/LWR analysis for etch process tuning. Lastly, we will discuss the benefits and drawbacks of each patterning stack and present an outlook on material selection for next-generation sub-36nm pitch architecture.
This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.