| AVS 66th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Tuesday Sessions |
| Session PS+EM-TuM |
| Session: | Advanced FEOL |
| Presenter: | Yohei Ishii, Hitachi High Technologies America Inc. |
| Authors: | Y. Ishii, Hitachi High Technologies America Inc. Y.-J. Lee, Taiwan Semiconductor Research Institute, Taiwan, Republic of China W.-F. Wu, Taiwan Semiconductor Research Institute, Taiwan, Republic of China R. Sugano, Hitachi, Ltd., Japan K. Maeda, Hitachi High Technologies America Inc. H. Ishimura, Hitachi High-Technologies Taiwan Corp., Taiwan, Republic of China M. Miura, Hitachi High Technologies, Japan |
| Correspondent: | Click to Email |
Many challenges have emerged due to down-scaling of device structure in order to follow Moore’s law. By modifying the transistor structure from planar to Fin-type Field Effect transistors (FinFETs), transistor electro-statics were improved, which led to overcoming short-channel effects. However, the change is no longer sufficient, and the semiconductor industry faces difficulty to further improve the transistor performance. One of the promising candidates for the improvement in sub-10nm process is to utilize Silicon/Silicon-germanium (Si/SiGe) dual channel FinFETs (Si in n-FETs and SiGe in p-FETs). In this case, simultaneous etching of Si and SiGe is required [1]. However, etch rate of SiGe is greater than Si for halogen chemistries commonly used in Si etch. Therefore, it is required to develop selective Si etch over SiGe for etch rate control between these two materials.
In order to maximize electrical performance of SiGe, modifying the SiGe surface composition into Si-rich surface at SiGe/gate-oxide interface is critical to reduce interface state density due to the impact on sub-threshold characteristics [2]. Traditional methods to produce Si-rich surface are epitaxial growth of Si cap over SiGe fin [3] and GeOx-scavenging process [4]. However, thermal budgets of these methods are relatively high, and there are concerns of strain relaxation in SiGe channel and Ge diffusion into Si substrate, both of which deteriorate the FET characteristics. Hence, a low-temperature process to produce Si-rich surface is required.
In this presentation, we will present two phenomena; one is Si-SiGe selective etch control, and the other is SiGe surface composition modification of SiGe into Si-rich surface by low temperature plasma. We will first present a plasma process, which etches Si selective to SiGe for Si-SiGe etching control, and will discuss the etching mechanism of the selective etching. We will then present the composition modification into Si-rich surface by utilizing Si segregation from the low temperature plasma process. This plasma etch technique can solve the etch rate control and surface composition challenges, which can be a promising scheme for realizing well-controlled SiGe finFETs with improved characteristics.
[1]. Y. Ishii et. al., Jpn. J. Appl. Phys. 57, 06JC04 (2018).
[2]. C. H. Lee et. al., IEDM Tech. Dig., p.31.1.1., 2016
[3]. H. Mertens, et al., VLSI Tech. Dig., p.58, 2014
[4] C.H. Lee, et. al., VLSI Tech. Dig., p. 36, 2016