| AVS 66th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Tuesday Sessions |
| Session PS+EM-TuA |
| Session: | Advanced BEOL/Interconnect Etching and Advanced Memory and Patterning |
| Presenter: | Angélique Raley, TEL Technology Center, America, LLC |
| Authors: | A. Raley, TEL Technology Center, America, LLC K. Lutker-Lee, TEL Technology Center, America, LLC X. Sun, TEL Technology Center, America, LLC Y.-T. Lu, TEL Technology Center, America, LLC Q. Lou, TEL Technology Center, America, LLC N. Joy, TEL Technology Center, America, LLC M. Edley, TEL Technology Center, America, LLC K. Taniguchi, TEL Miyagi Limited, Japan M. Honda, TEL Miyagi Limited, Japan P.E. Biolsi, TEL Technology Center, America, LLC |
| Correspondent: | Click to Email |
As logic nodes continue to scale below 7 nm, the back-end-of-line (BEOL) critical pitch has moved to sub-40 nm and is forecasted to scale down to 14 nm according to the latest International Roadmap for Devices and System (IRDS). This aggressive scaling has led to an industry wide effort in terms of materials research to manage interconnect resistance, patterning innovations to control for process variation impact and an increased focus on self-limited or highly selective processes.
In addition to the patterning and integration complexities that arise with scaling, pitch reduction has a direct impact on the plasma etch-processing window. Conventional continuous wave processes can no longer achieve stringent aspect ratio dependent etching (ARDE), selectivity and profile control requirements and have gradually given way to pulsed plasma processes, decoupled process sequence plasmas or remote plasmas to widen the process space.
In this talk, we will give an overview of plasma etching challenges and solutions for the BEOL in terms of patterning integration, dielectric etch and new materials introduction.