| AVS 65th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS+EM-WeM |
| Session: | Advanced Patterning |
| Presenter: | Yohei Ishii, Hitachi High Technologies America Inc. |
| Authors: | Y. Ishii, Hitachi High Technologies America Inc. Y.-J. Lee, National Nano Divice Laboratories W.-F. Wu, National Nano Device Laboratories K. Maeda, Hitachi High Technologies America Inc. H. Ishimura, Hitachi High-Technologies Taiwan Corp. M. Muira, Hitachi High-Technologies Corp. |
| Correspondent: | Click to Email |
As a consequence of downscaling to follow Moore’s law, device structure was changed from conventional planar structure to Fin-type Field Effect Transistors (FinFETs) to achieve higher drive current and lower leakage current. In sub-10nm processes, it is necessary to further improve FinFETs electrical performance. A promising approach is to replace silicon fins with a new material, such as silicon germanium, which enhances carrier mobility [1]. In Si/SiGe dual channel FinFETs, Si is used in n-FETs, while SiGe is used in p-FETs. Therefore, it is necessary to understand the difference in etching characteristics between Si and SiGe. Recently, we have developed an etching process to selectively etch Si over SiGe, and proposed the etching mechanism [2]. This etching technique proved to adjust not only the Si and SiGe pattern CDs (Si CD> SiGe CD and vice versa), but also Si and SiGe etched depth (Si etched depth < SiGe etched depth and vice versa), using Si/SiGe dual channel fin pattern samples.
As for the electrical performance of SiGe, it is important to form Si-rich SiGe surface at the SiO2/SiGe interface, because interface states play important role on sub-threshold characteristics [3]. There are several methods to form Si rich surface, such as thin Si cap epitaxial growth over SiGe fin [4] or H2 anneal-induced Si segregation [5]. However, it remains difficult to achieve the surface without the formation of a thick Si layer, which acts as a parasitic channel. In addition to that, avoiding Ge diffusion into Si cap layer is also an issue.
In this presentation, we propose a low-temperature process for achieving atomically controlled Si rich surface by utilizing plasma treatment to induce SiGe composition modulation at SiGe surface. We will also present a method to flexibly control the composition of SiGe surface (from Ge-rich surface to Si-rich surface) by utilizing plasma treatments. Details of the study will be discussed in this presentation.
[1] D. Guo, et. al., VLSI Tech. Dig., p.14, 2016
[2]. Y. Ishii et. al., Jpn. J. Appl. Phys. (Accepted)
[3]. C. H. Lee et. al., IEDM Tech. Dig., p.31.1.1., 2016
[4]. H. Mertens, et al., VLSI Tech. Dig., p.58, 2014
[5] L. Rudkevich, et. al., Phys. Rev. Lett. Vol.81 p. 3467 (1998)