| AVS 65th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS+EM-WeM |
| Session: | Advanced Patterning |
| Presenter: | Patricia Pimenta Barros, CEA-LETI, France |
| Authors: | P. Pimenta Barros, CEA-LETI, France N. Posseme, CEA, LETI, France S. Barnola, CEA-LETI, France R. Tiron, CEA-LETI, MINATEC, France A. Gharbi, CEA-LETI, France MA. Argoud, CEA-LETI, France Z. Chalupa, CEA-LETI, France M.-G. Gusmao-Cacho, CEA-LETI, France A. Paquet, Arkema, France F. Delachat, CEA-LETI, France C. Nicolet, Arkema, France C. Navarro, Arkema, France |
| Correspondent: | Click to Email |
The continuous increase of CMOS device density has led to new 3D architectures. For the sub-7nm nodes, Leti investigates the interest of Tri-gate, Ω-gate and stacked nanowires architectures for better electrostatic control at aggressive dimensions [1, 2]. These new architectures bring a set of etching challenges at the integration level (from active, spacer, Si/SiGe removal) and require innovative etching solutions, such as gas or bias pulsing and atomic layer etching (ALE). In this paper, an overview of the main challenges and solutions for Si/SiGe stacked NW patterning will be exposed.
The active patterning of dense stacked nanowires have been already demonstrated by Leti using the Sidewall Image Transfer (SIT) technique [3]. In this paper, we will focus on the Directed Self Assembly (DSA) of block-copolymers (BCPs) that is considered as a cost-effective and complementary solution to conventional or EUV lithography [4, 5]. Herein, stacked Si nanowires are patterned using a DSA UV-assisted graphoepitaxy approach. Chemoepitaxy and graphoepitaxy approaches, which are the two ways to perform DSA, will be benchmarked. The transfer of ultra-small patterns using high-chi BCPs materials (pitch <20nm) will be also reported.
Based on LETI’s FDSOI background, we are investigating new architectures such as steep slope devices, mechanical switches or single electron devices in a CMOS compatible flow. They are all studied in a CMOS co-integration perspective to enable the hybrid logic field [6]. In this paper, we will show that DSA patterning could be a good candidate for some applications beyond CMOS such as Single Electron Transistor devices or nano-membranes manufacturing.
[1] Coquand, R., et al., Symposium on VLSI Technology, pp. T226-T227 (2013)
[2] Barraud, S., et al., Symposium on VLSI Technology, Kyoto, pp. T230-T231 (2013)
[3] Gaben, L., et al., International Conference on Solid State Devices and Materials, 1108 - N-2-2, pp1108-1109 (2015)
[4] Jeong, S-J., et al., Materials today 16 (12), 468-476 (2013).
[5] Guerrero, D. J., Solid State technology (2017)
[6] Barnola, S, et al., Proc. SPIE 9054 (2014)