| AVS 65th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS+EM-WeM |
| Session: | Advanced Patterning |
| Presenter: | Jin Won Lee, Samsung Electronics, Republic of Korea |
| Authors: | J.W. Lee, Samsung Electronics, Republic of Korea J.Y. Lee, Samsung Electronics, Republic of Korea K.J. Seong, Samsung Electronics, Republic of Korea T.S. Kwon, Samsung Electronics, Republic of Korea H.H. Jeong, Samsung Electronics, Republic of Korea S.S. Hong, Samsung Electronics, Republic of Korea D.W. Han, Samsung Electronics, Republic of Korea B.R. Lim, Samsung Electronics, Republic of Korea A.R. Ji, Samsung Electronics, Republic of Korea Y.M. Oh, Samsung Electronics, Republic of Korea J.C. Park, Samsung Electronics, Republic of Korea |
| Correspondent: | Click to Email |
As the Critical Dimension (CD) of Semiconductor becomes smaller, process using new materials is being developed and multi-patterning processes are required to overcome the limitations of lithography. However, only a few of them have been adapted to mass-production of the semiconductor because they costs highly and are complex. As a result, Researches on Si materials (SiN, SiO2, Poly-Si) widely used in semiconductors have been actively conducted.
In this study, we will describe the etch process with excellent LER (~ 1) by removing the distortion which causes various problems and securing the vertical profile in the Poly-Si nano hole with the high aspect ratio (1:50) in sub X nm. HBr based Etch is favorable for Poly Si Etch because it has a high selectivity between Poly-Si and SiO2. However it has tendency to cause clogging SiXBrYOZ byproducts which aggravate the open margin and profile control. By the way, the etch profile is also deteriorated due to irregularly crystallized grains, which is a character of Poly-Si and they might induce etch stop it is severe. Unlike HBr based etch, Cl2 based etch tends to be less polymerizing and less reactive thus it causes less clogging which is less effective by the poly grain and is effective to improve the profile. We adopted Cl2 based multi cycle etch over HBr based etch to secure the characteristics of the vertical profile with etch stop free.
Distortion must be solved in order to improve the LER, which is an important factor that affects not only the vertical profile but also the electrical characteristics of semiconductor of device. In general, the etch rates increases with increased process temperature and the distortion tends to be improved. However, in our study, the hole distortion is improved and more vertical profile is led at low temperature. This can be explained by the difference in the re-deposition tendency of byproduct. When the temperature is high, a large amount of byproduct, that occurs after etch, is more re-deposited on the upper part than the lower part because the convective phenomenon becomes more active and the sticking coefficient of the hole side wall decreases. As a result, the clogging becomes worse, and the hole side wall cannot be re-deposited uniformly. CD tends to be smaller. Profile tends to be positive and LER tend to be worse. On the contrary, if the process temperature is low, the sticking coefficient of the hole side wall increases, and the re-deposition is performed well. Since it is totally re-deposited in the hole side wall, it is confirmed the CD is increased and a vertical profile is foamed and the LER is improved.
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