Paper PS+EM-WeM10
Precise Control of Silicon Nitride Spacer Etching Selectively to Silicon for 3D CMOS Device

Wednesday, October 24, 2018, 11:00 am, Room 104A

With transistors size scaling down, device processing requirements become more and more stringent. For technology node beyond 14 nm, one of the most critical step is the spacer etching. It requires a perfect anisotropy (no CD loss) without damaging [1] nor consumption of the exposed material like silicon, silicon germanium and oxide [2,3]. In planar transistor, the silicon or silicon germanium consumption is limited by the short over-etch process (30-50%). However for vertically stacked wires3D devices, the silicon fin is directly exposed during the removal of the silicon nitride on the active area sidewalls. This is the major issue since in this case, important over etch is required (>200%) to fully remove the residues at the bottom of the fin. Therefore, the spacer etch is considered today as one of the most challenging etch process for 2D but more especially 3D devices.

Today, current fluorocarbon etch chemistry (like CH3F/CH4/O2) are no longer suitable for 3D CMOS integration where long overetch is necessary.

In this context, we propose to introduce a new cyclic etch process of silicon nitride selectively to silicon to fulfill the stringent etch requirements described above [4].

This cyclic process is composed of two steps. A first step consists in silicon nitride etching till to top of the silicon fin. XPS analyses performed on blanket films (Silicon nitride and Si) reveal that a thin reactive layer is formed at the SiN surface, while an important deposition is observed at Si surface. This deposition at the Si surface is dependent of the process time. A second step (CHF3 based chemistry) allows partially removing the deposition on top of Si while etching the silicon nitride. Thanks to this new approach silicon nitride is linearly etched as a function of the number of cycles while the silicon film consumption is below 1.5nm. The selectivity reached by this new process is >100.

The impact of the different process step times and number of cycles on SiN and Si surface composition has been analyzed by XPS and will be presented. A proof of concept on vertically stacked wires patterned wafer will show that the silicon nitride spacer can be fully removed on the sidewall of the fin with limited impact on the silicon consumption/damage.

[1] N. Kuboi, T. Tatsumi, T. Kinoshita, T. Shigetoshi, M. Fukasawa, J. Komachi, and H. Ansai, J. Vac. Sci. Technol. A 33 (6), 061308 (2015).

[2] B. E. E. Kastenmeier, P. J. Matsuo, and G. S. Oehrlein, J. Vac. Sci. Technol. A 17 (6), 3179 (1999).

[3] K. Eriguchi, Y. Nakakubo, A. Matsuda, Y. Katao, K. Ono, IEEE Electr. Device L. 30 (7), 712 (2009).

[4] N.Posseme, S.Barnola, patent pending