AVS 65th International Symposium & Exhibition
    Plasma Science and Technology Division Wednesday Sessions
       Session PS+EM-WeA

Paper PS+EM-WeA9
Gas-phase Pore Stuffing for Low-damage Patterning of Organo-silicate Glass Dielectric Materials

Wednesday, October 24, 2018, 5:00 pm, Room 104C

Session: Advanced BEOL/Interconnect Etching
Presenter: Jean-Francois de Marneffe, IMEC, Belgium
Authors: J.-F. de Marneffe, IMEC, Belgium
M. Fujikama, Tokyo Electron Technology Solutions Limited
T. Yamaguchi, Tokyo Electron Technology Solutions Limited
S. Nozawa, Tokyo Electron Technology Solutions Limited
R. Niino, Tokyo Electron Technology Solutions Limited
N. Sato, Tokyo Electron Technology Solutions Limited
R. Chanson, IMEC, Belgium
K. Babaei Gavan, IMEC, Belgium
A. Rezvanov, IMEC, Belgium/Moscow Institute of Physics and Technology
F. Lazzarino, IMEC, Belgium
Z. Tokei, IMEC, Belgium
Correspondent: Click to Email

Capacitance gain remains of high value for lowering the interconnect RC delay in CMOS transistors, especially in the current design-technology co-optimization (DTCO) era where circuit density is maximized. In view of their superior mechanical properties, intermediate low-k dielectrics (sub-nanometer pore diameter, open porosity < 20%, k-value > 2.5) do attract nowadays most interest. CVD porous organo-silicate glasses are the most industry-relevant materials. They do suffer from processing damage, due to their porous and bi-component nature. As a consequence, some tailored protection strategies need to be developed. The gas-phase pore stuffing (GPPS) is a CVD method using two organic reactive precursors. Vaporized monomers (Gases A and B) are injected into the reactive chamber, supplied to the substrates and polymerized. Polymers are formed in the pores, deep in the bulk dielectrics, and can be removed by thermal annealing in controlled atmosphere. The GPPS technique is demonstrated on multiple OSG materials (various porosity), then applied to an OSG dielectric with nominal k-value 2.55, porosity ~ 16% and pore diameter ~ 0.8nm, which is embedded into a M1/V0 45nm ½ pitch vehicle. The target patterning sequence aims at creating a dual damascene structure by the fully self-aligned via approach (FSAV). The benefits of the GPPS is studied on the various plasma steps used in the FSAV patterning, allowing to reduce plasma damage up to 50% for the most damaging part of the FSAV patterning sequence (CO2 ash, used for post-via strip, GPPS recess and GPPS unstuffing). The ability of the GPPS to form a protective plug is demonstrated, by excess polymerization in the pre-patterned via. By taking advantage of the specific properties of the GPPS approach, modifications of the FSAV patterning sequence are proposed, leading to potentially large capacitance gain. Various unsealing, unplugging and unstuffing options will be described, aiming at preparing the low-k surface for GPPS stuffing, and/or restoring the original porosity without residues, at the end of the patterning sequence. The gain in low-k dielectric properties, using the GPPS technique, is studied by k-value extraction on the various used vehicles.

Dr R. Chanson has received funding from the European Union’s Horizon 2020 research and innovation programme under the Marie Sklodowska-Curie grant agreement No 708106.