| AVS 65th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS+EM-WeA |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | Xiang Hu, GLOBALFOUNDRIES |
| Authors: | X. Hu, GLOBALFOUNDRIES Y. Ren, GLOBALFOUDRIES D. Medeiros, GLOBALFOUNDRIES P. Lee, GLOBALFOUNDRIES |
| Correspondent: | Click to Email |
As the semiconductor features progressively shrink to sub 20 nm dimensions, patterning technology becomes significantly more critical. Pattern fidelity, yield, quality and cost now all incrementally become competing factors to the successful production of advanced technology nodes in high volume manufacturing. In this paper we will provide an overview on the challenges of patterning technology for single patterning, double patterning (DP), triple patterning (TP), self-aligned double patterning and EUV patterning, based on the learning of BEOL (Back End of Line) patterning technology development. We will focus on BEOL patterning technology challenges for 14nm high volume manufacturing, and demonstrate the patterning solutions for DP and TP 1D and 2D structure optimization. We will elaborate on process enhancements and controls such as CD, tip-to-tip and iso-dense loading optimization, the integrated patterning solution for open and short yield improvement and via-to-metal reliability improvement, the multi-variant APC control for process stability improvement by APC thread reduction and thread sharing among a variety of products. The success of BEOL patterning technology is dependent on patterning capability, process robustness and cost of patterning solutions.