Paper PS+EM-WeA10
ALD-Sequential Etch to Address Advanced BEOL Etch/Integration Challenges

Wednesday, October 24, 2018, 5:20 pm, Room 104C

As semiconductor nodes continue to scale past 7nm and beyond, control of critical dimension (CD), reactive ion etch (RIE) lag, low-k damage, material selectivity and chamfer profile becomes increasingly challenging for patterning of low-k materials in back end of line (BEOL) dual damascene processes. While modulation of plasma processing can address some of these challenges, process knobs that benefit one parameter can come into conflict with another, thereby leading to a necessity to compromise between them.

Recently, the introduction of anisotropic sequential etch, in which cyclical alternation of separated deposition and activation (etching) steps are used to decouple and control plasma chemistry, has revealed additional flexibility in profile control. However, anisotropic sequential etch tends to benefit processes that require significant boosts in etch selectivity and a controlled directional etch rate, while showing little improvement for processes where material damage is also a major concern, as in the case of low-k. As such, alternative methods to protect the low-k sidewall/corner during dual damascene processing are necessary. Introduction of a conformal, sacrificial side wall/corner protective layer through atomic layer deposition (ALD) can potentially fill this gap. Addition of an ALD-sequential etch process allows for a wide range of deposition choices, in contrast to the limited options generated through the gas chemistries typical for plasma etch. In this talk, we show how an ALD-sequential etchcan address dielectric etch challenges.