| AVS 65th International Symposium & Exhibition | |
| Plasma Science and Technology Division | Wednesday Sessions |
| Session PS+EM-WeA |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | Jeffrey Shearer, IBM Research Division, Albany, NY |
| Authors: | J.C. Shearer, IBM Research Division, Albany, NY A. Raley, TEL Technology Center, America, LLC Q. Lou, TEL Technology Center, America, LLC J. Kaminsky, TEL Technology Center, America, LLC L. Meli, IBM Research Division, Albany, NY |
| Correspondent: | Click to Email |
As EUV lithography takes center stage in next-node semiconductor logic manufacturing, many challenges still need to be overcome. Of those, resist scumming, resist line breaks, and pattern roughness stand out as three of the top issues to address, especially when direct printing single levels below 36nm pitch. Previously, we have reported several methods of addressing these concerns in BEOL patterning, including introducing new material stacks and implementing new etch techniques such as resist reinforcement and quasi-atomic layer etching (QALE). This presentation will expand upon those ideas as well as introduce new etch methods that help enable direct EUV printing of single levels. Resist scumming will be addressed by exploring different types of descum etch chemistry. Data will show that line breaks can be reduced by resist reinforcement methods using pre-etch in situ deposition, increasing etch selectivity using QALE, and implementing direct current superposition (DCS). Additionally, we will show how line end pullback can be modulated with these different techniques and data will be presented that show resist reinforcement methods can recover more than 50% of line end pullback caused by more selective etch chemistries. The aspect ratio dependence of resist reinforcement and QALE will be discussed along with how aspect ratio impacts pattern roughness. The effectiveness of all of these etch strategies will be evaluated with defect characterization (bridge patterns and line breaks) and electrical testing (shorts and opens yield). Finally, we will discuss the impact of chamber configuration on EUV lithography pattern transfer. Data will be shown from chambers with the radio frequency (RF) split between top and bottom electrodes, dual RF on the bottom electrode only, and RF split between top and bottom electrodes with the addition of DCS. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.