Paper PS+EM+SE-TuM2
III-V/Ge Heterostructure Etching for Through Cell Via Contact Multijunction Solar Cell

Tuesday, October 23, 2018, 8:20 am, Room 104A

Through cell via contact architecture aims to increase the multijunction solar cell efficiency by 3% and the power yield per wafer by 20% by transferring the front side contact to the backside using insulated and metallized vias. Via hole plasma etching through the III-V/Ge heterostructure is a key step to fabricate this new architecture. It is challenging, as dozens of layers must be anisotropically etched with low roughness and free damage to ensure optimal cell performance. Moreover, etched patterns must have a depth of >30 µm and present >3 aspect ratio. In this abstract, several patterning strategies are presented to address these challenges.

The epiwafers consist of a 8µm-thick III-V heterostructure (InGaP, InGaAs, GaAs, AlInP, AlGaAs, AlGaInP layers and quantum dots) epitaxially grown on Ge substrate. A 5µm thick SiO₂ hard mask (HM) is first deposited by PECVD and patterned by contact photolithography and plasma etching. The optimization of both the lithography and HM opening steps is crucial for an optimal transfer into the III-V/Ge layers. It is observed that sloped and rough hard mask sidewalls after the HM opening step are detrimental to the via hole etching and lead to severe damage on the heterostructure sidewalls. Combining a thick photoresist mask with vertical sidewalls and an optimized Ar/C₄F₈/O₂ plasma process developed in a capacitive coupled plasma reactor allows to pattern the 5µm-thick HM with vertical and quite smooth sidewalls.

A room temperature SiCl₄/Cl₂/H₂ plasma process was developed in an inductively coupled plasma reactor to etch vias in the III-V/Ge heterostructures. The cell performance loss associated to via etching was almost absent, indicating that such chemistry is suitable for photovoltaic applications. However, some layers present isotropic etching, which is problematic for the via insulation and metallization. Indeed, III-V compounds with low indium concentration are more sensitive to lateral etching, thus creating preferential isotropic etching in several III-V layers. This represents a challenge considering the aspect ratio and the depth targets. Indeed, lateral etching will be even greater for a longer process time. To obtain anisotropic etching, a high temperature (200°C) SiCl₄/Cl₂/H₂ process is proposed. The enhanced volatility of the indium by-products combined with the Si-based passivation could improve the anisotropy while maintaining optimal cell performance. FIB-TEM and EDX are performed to characterize both the etch morphology and the passivation layer. Moreover, optoelectrical measurements will assess the cell performance after via etching.