AVS 65th International Symposium & Exhibition
    Plasma Science and Technology Division Tuesday Sessions
       Session PS+EM+SE-TuM

Paper PS+EM+SE-TuM1
Development and Understanding of Isotropic Etching Process of Si Selectively to Si0.7Ge0.3

Tuesday, October 23, 2018, 8:00 am, Room 104A

Session: Plasma Processing of Challenging Materials - I
Presenter: Sana Rachidi, CEA-LETI, France
Authors: S. Rachidi, CEA-LETI, France
A. Campo, CEA-LETI, France
V. Loup, CEA-LETI, France
N. Posseme, CEA, LETI, France
J.M. Hartmann, CEA-LETI, France
S. Barnola, CEA-LETI, France
Correspondent: Click to Email

The vertically stacked wires MOSFET architecture pushes further the scaling limits of the CMOS technology. Now deemed as a possible extension to FinFET, it offers multiple benefits. A low IOFF current is indeed expected, thanks to multi-gate electrostatic control, with a high current drivability due to 3D vertically stacked channels.

The fabrication starts with the epitaxial growth of (Si0.7Ge0.3/Si) multilayers (8-12 nm for Si and SiGe layers) on blanket SOI substrates. Then, individual and dense arrays of fins were patterned to fabricate stacked-NWs FETs with 40 nm-pitch fins which are 36 nm high and roughly 20 nm wide. After that, dummy gates and spacers are defined prior to the anisotropic etching of the (Si/SiGe) multilayers. Today one of the most critical step in such device realization is the isotropic silicon removal selectively to silicon germanium.

In this study an understanding of selectivity evolution between Si and SiGe as a function of CF4/O2/N2 remote plasma parameters is presented. The experiments performed on 300mm blanket wafers (Si and Si0.7Ge0.3) have been carried out on CDE-Allegro.

The impact of etching parameters (CF4, O2, N2, microwave-power, pressure and temperature of the electrostatic chuck) and different pre-treatments on etching rates and selectivity is first investigated. X-ray photoelectron spectroscopy (XPS) analyses will show that for Silicon, a SiOxFy thick reactive layer is formed on the etched surface and controls its etching regime. As for Si0.7Ge0.3, a passivation layer of 2 nm is observed. And it contains a mixture of GeOx and SiOxFy species.

Based on these results, application to patterned wafers will be shown. Scanning Electron Microscopy (SEM), Transmission electron microscopy (TEM) and Energy Dispersive X-ray Spectroscopy (EDX or EDS) are here used for the pattern characterisation.

* Corresponding author e-mail: sana.rachidi @cea.fr [mailto:sana.rachidi@cea.fr]