AVS 65th International Symposium & Exhibition
    Advanced Ion Microscopy Focus Topic Thursday Sessions
       Session HI-ThP

Paper HI-ThP2
Focused Cs Ion Beam-Induced Deposition and Gas Assisted Etch Characterization Results for 10nm Circuit Edit Applications

Thursday, October 25, 2018, 6:00 pm, Room Hall B

Session: Advanced Ion Microscopy Poster Session
Presenter: Roy Hallstein, Intel Corporation, USA
Authors: R.M. Hallstein, Intel Corporation, USA
R.H. Livengood, Intel Corporation, USA
M.P. Ly, Intel Corporation, USA
Y. Greenzweig, Intel Corporation, Israel
Y. Drezner, Intel Corporation, Israel
B.J. Knuffman, zeroK NanoTech
A.V. Steele, zeroK NanoTech
A.B.J. Knuffman, zeroK NanoTech
Correspondent: Click to Email
Focused Ion Beam Gas Assisted Etch (GAE) and Ion Beam Induced Deposition (IBID) are used extensively in Circuit Edit nanomachining. Historically the Gallium Focused Ion Beam (FIB) has been the primary ion source technology for Circuit Edit applications. [1, 2] More recently, the neon and nitrogen (N2) gas field ion sources (GFIS) have also been introduced to enable very small, high precision nanomachining for circuit rewiring and mask defect repairs respectively. [3, 4, 5] Other emerging ion source technologies are the so-called ‘cold ion’ sources, which ionize atoms that have been laser-cooled to micro-kelvin temperatures. These sources have been shown to have high brightness and low energy spread, enabling small focal spot sizes. [6] Two such emerging ‘cold’ sources that produce cesium ion beams are under development by zeroK NanoTech Corporation and Tescan Orsay Holding. [7, 8]

As part of the due diligence to identify breakthrough ion beam technologies to keep pace with nanomachining applications scaling requirements, we have completed preliminary analysis of the attributes of cesium for Circuit Edit applications. In this paper, Proof of Concept 10nm Circuit Edit results using the zeroK Nanotech Cesium ion beam-based GAE and IBID will be presented. Preliminary results include GAE chemical etching of semiconductor materials and IBID results for dielectric and metal depositions. Finally, preliminary electrical test results of proof of concept Circuits Edits on 10nm process node will be presented.