| AVS 63rd International Symposium & Exhibition | |
| Plasma Science and Technology | Wednesday Sessions |
| Session PS-WeA |
| Session: | Atomic Layer Etching and Low Damage Processing |
| Presenter: | Christopher Brennan, MIT Lincoln Laboratory |
| Authors: | C. Brennan, MIT Lincoln Laboratory C. Neumann, MIT Lincoln Laboratory S. Vitale, MIT Lincoln Laboratory |
| Correspondent: | Click to Email |
Metal gate materials have now replaced polysilicon gates for advanced silicon CMOS fabrication of both planar silicon MOSFETs and FinFETs. However, plasma processes employed for metal gate deposition can cause significantly more damage to the gate dielectric material than with traditional chemical vapor deposition polysilicon gates, resulting in reduced device performance and reliability. Titanium nitride (TiN) is one such metal gate material, possessing both thermal stability and compatibility with gate dielectric materials. Additionally, the workfunction of TiN can be tuned to make mid-gap metal gates for undoped-body fully depleted silicon-on-insulator (FDSOI) transistors for subthreshold, ultra-low power operation. Gate dielectric quality remains critical for advanced device fabrication, especially for these low power, low leakage devices.
This work compares plasma-induced gate oxide damage by two different metal gate deposition processes: magnetron sputtering and plasma-enhanced atomic-layer-deposition (PE-ALD). FDSOI transistors fabricated with either gate deposition process showed similar electrostatic performance, with good short channel performance including subthreshold swing, DIBL, and Vt roll-off. However, gate dielectric quality metrics were significantly better when PE-ALD TiN was used compared to plasma sputtered TiN. CV measurements exhibited stretching of the curves and increased hysteresis with sputtered TiN compared to PE-ALD TiN, indicative of a higher density of interface states in the former case. In addition, gate leakage was 1200x higher for the plasma sputtered TiN devices, which is consistent with a high density of defects in the gate oxide leading to trap-assisted tunneling. Finally, transistors fabricated with both methods show that those fabricated with PE-ALD TiN demonstrate a significantly lower gate oxide failure probability.
Taken together, the electrical results suggest that plasma sputtering damages the gate dielectric through energetic ion and vacuum ultra-violet (VUV) photon bombardment which breaks Si-O bonds and leaves defect states. In addition to higher leakage, these defect states can lead to device reliability issues and high early failure rates. Alternatively, inductively coupled plasma PE-ALD produces a much lower energetic ion and VUV flux at the wafer surface, resulting in markedly less damage. Instead of damaging the gate oxide, PE-ALD initially deposits a sub-nm TiOCN film which may serve as a passivating layer. This layer does not seem to induce any undesirable device characteristics except for a slight increase in EOT.