Paper PS-ThP33
Magnetic Tunnel Junctions Etch and Encapsulation Process Optimization for High-Density STT-MRAM Applications

Thursday, November 10, 2016, 6:00 pm, Room Hall D

STT-MRAM is being extensively developed as a potential candidate to replace conventional memories due to its unique characteristics: fast speed, non-volatility and excellent endurance. One of the major challenge for high-volume, high density STT-MRAM fabrication remains the patterning of the Magnetic Tunnel Junction (MTJ). Practically, the metals used in the MTJ stack hardly form any volatile compounds with conventional etching plasmas often resulting in strong re-deposition of metals on the sidewall (SW) of the junction and hence shorting of the device. Moreover, MTJs manifest strong sensitivity to any form of chemical or physical damage caused by plasma processing leading to degradation of the electrical/magnetic performance of the fabricated memory cell. The focus of this work is to develop a Reactive Ion Etching based patterning process in combination with SW engineering by oxidation and in-situ encapsulation to mitigate those issues. We demonstrated patterning of MTJ down to 30nm, in pitch down to 200nm with excellent electrical yield and very limited performance degradation.

The MTJ patterning process has been developed on a TACTRAS platform from Tokyo Electron Limited using a dual-frequency capacitive coupled plasma reactor specially customized for STT-MRAM application as well as a microwave plasma CVD reactor to deposit Si₃N₄. A TiN metallic hard mask has been used to pattern the CoPt or CoNi based MTJs with perpendicular magnetic anisotropy. The patterning consisted of a 2-step sputtering based etch process. The first etch was carried out with Ar to define the MTJ pillar while the second etch used Kr to efficiently remove metallic residues from the MTJ SWs. Noble gases were used in order to avoid chemical damage. The patterning was followed by an in-situ mild oxidation of the MTJ SWs to passivate metallic residues as well as the peripheral damaged zone caused by ion bombardment. Finally, a Si₃N₄ encapsulation was applied in-situ to protect the MTJ from air exposure.

We demonstrated isolated pillar size down to 30nm as well as 45nm pillars at a 200nm pitch. Tight RP distribution (σ~4%) was achieved demonstrating that pillar size was uniform across the wafer surface and the MTJ short were efficiently circumvented. Limited degradation (<10%) of the TMR as function of pillar size was achieved. A yield of more than 97% was achieved in Mbit array with less than 0.5% cells exhibiting electrically shorted behavior and the 2.5% remainder of the cell being not switchable. The optimization of the Si₃N₄ encapsulation process to improve the thermal stability of the device post processing will be discussed at the conference.