Paper PS-ThP18
New Deep SiO₂ Etching Process Issues for Silicon Photonics Device Fabrications

Thursday, November 10, 2016, 6:00 pm, Room Hall D

Silicon Photonics (SiPh) is a promising technology for wide-band and large-capacity data communications. The SiPh chip needs to embed laser diodes (LD’s) for optical communication. In our approach, LD’s have to be mounted on a pedestal structure [1, 2]. To fabricate the pedestal structure, 5 µm deep SiO₂ hole should be patterned by a deep etching process.

A 300 mm CCP etch system was applied to etch the SiO₂ layer. Photoresist (PR) patterns with 4.6 µm thick were developed by a KrF lithography system. Ar diluted fluorocarbon gas chemistries were adopted. Three etch-selectivity conditions for the SiO₂ against the PR were examined. Significant etch residues over the etched surface were observed under a relatively high etch selectivity condition. In contrast, the sample etched under a relatively low etch selectivity condition showed no etch residues, but showed conspicuous striations at the sidewalls of SiO₂ which can cause optical coupling loss of the SiPh devices. These deep SiO₂ etching issues as a function of the etch selectivity can be discussed qualitatively.

Under the high etch selectivity condition, deposited fluorocarbon polymer and etch by-products over the chamber walls increase generally. They can re-deposit over the wafer surface during etching, and cause the etch residue. The amount of the deposition (DP) can be expressed as follows,

DP = f(t),

where t is total etching time, and f is a function which reflect the etch selectivity. Higher the etch selectivity is, larger the DP is. The etch residue issue will happen when the DP value exceeds some threshold. This is a common issue in fabricating both CMOS and SiPh chips.

On the other hand, the etching under the lower etching selectivity condition brings about larger damages on PR polymer by bond breaking and desorption of functional groups, and causes the large line edge roughness (LER) of the PR pattern which will be transferred to the striation during etching. The LER can be expressed as follows,

LER = g(t),

where g is a function related to the etch selectivity reflecting protective ability for the PR. Higher the etch selectivity is, smaller the LER is at the same t. This issue is apparent for the SiPh chip fabrication.

Therefore, it is important to minimize DP·LER products within some threshold in the deep SiO₂ etching process developments for the SiPh devices. And, we succeeded in the deep SiO₂ etching by the DP·LER products minimization approach.

This work was supported by NEDO. The authors thank staff members of SCR station in AIST for their technical support. [1] T. Shimizu, et al., Photon. Res., 2, A19 (2014). [2] K. Kinoshita, et al., AVS 62th Int. Symp., PS-ThP8, p. 51, (2015).