AVS 63rd International Symposium & Exhibition | |
Plasma Science and Technology | Thursday Sessions |
Session PS-ThP |
Session: | Plasma Science and Technology Division Poster Session |
Presenter: | Vincent Ip, Veeco |
Authors: | V. Ip, Veeco S. Huang, Lam Research Corporation S.D. Carnevale, Veeco I.L. Berry, Lam Research Corporation K. Rook, Veeco T.B. Lill, Lam Research Corporation A.P. Paranjpe, Veeco F. Cerio, Veeco |
Correspondent: | Click to Email |
STTRAM device patterning has been demonstrated via either: reactive ion etch followed by ion beam etch (IBE); or by a full IBE strategy.[1],[2] The patterning of high density STTRAM structures requires detailed process optimization, due to multiple requirements including: high aspect ratio; avoidance of shorting across the MTJ barrier; and minimization of damage to the active layers of the structure. We discuss methods to address each of these challenges under a full IBE patterning scheme. For large CD structures, with wide pitch, a single-step IBE recipe may be sufficient, but for small CD or tight pitch features, a multi-step IBE process appears to be necessary.
The primary consideration during the first etch step(s) is to effectively open up the pattern, while minimizing re-deposition across the tunnel junction. We present experimental IBE etch rates for typical STTRAM stack and hard mask materials versus: incidence angle; ion species (Neon, Argon, Xenon); and ion energy. We utilize these etch rates combined with 2-D etch simulations, to present guidelines for etching of STTRAM pillars with mask height ~ 150 nm, and pitch varying from 80 – 800 nm. The simulations capture etched feature shapes and spatial distribution of redeposited material. We show that re-deposition can be minimized by: etch angle further from normal incidence; using lower mass ion; and/or higher ion energy.
The primary consideration during the final etch step(s) is to remove any sidewall damaged layer resulting from the earlier step(s), while minimizing further damage.[3] We present 3-D etch calculations and SRIM simulations to provide guidelines for the damage cleanup steps, in terms of optimal etch angle, and optimal ion species and energy.[4] We show that sidewall damage cleanup is maximized by etch angle further from normal, while further damage generation is minimized primarily by lower ion energy. In particular, we present minimum ion energies required to maintain specified damaged layer thicknesses from <1nm upwards.
We simulate optimized combinations of multiple etch steps, and demonstrate effective patterning of pillars of 80 nm pitch, resulting in feature sidewalls with ~ 85o sidewall angle and no metal re-deposition across the tunnel junction.
[1] M. Gajek et al, Applied Physics Letters 100, 2012.
[2] Shigeki Takahashi et al, IEEE Transactions on Magnetics 42 (10), October 2006.
[3] Yuichi Ohsawa et al, International Magnetics Conference 2016, to be published IEEE Transactions on Magnetics.
[4] J. Ziegler, 1998, available at http://www.srim.org/