| AVS 63rd International Symposium & Exhibition | |
| Plasma Science and Technology | Monday Sessions |
| Session PS-MoM |
| Session: | Advanced FEOL/Gate Etching |
| Presenter: | John Sporre, IBM Research Division |
| Authors: | J.R. Sporre, IBM Research Division X. Liu, IBM Research Division, T.J. Watson Research Center S. Seo, IBM Research Division C. Prindle, GLOBALFOUNDRIES, Inc. P. Montanini, IBM Research Division R. Xie, GLOBALFOUNDRIES, Inc. M. Sankarapandian, IBM Research Division S. Mehta, IBM Research Division M. Breton, IBM Research Division S. McDermott, IBM Research Division S. Kanakasabapathy, IBM Research Division B. Haran, IBM Research |
| Correspondent: | Click to Email |
Continued scaling of FinFET technology introduces unique challenges with respect to patterning high aspect ratio structures. In addition to the traditional challenge of etching a gate with uniform sidewall and cross wafer uniformity, new challenges are introduced as a result of the reduction of inter-gate spacing. Maintaining selectivity to dielectrics during Si etch can result in profile degradation due to etch polymer by-product pinch-off. Low polymer producing chemistries can prevent this pinch-off, but with the cost of unacceptable Fin erosion. Furthermore, gate profile and pitch control can have significant impact on down stream process stability and may result in downstream gate bending. In this paper, the unique challenges caused by gate pitch scaling will be explored with respect to not only their impact on downstream functionality, but also to the gate etch itself.