Invited Paper PS-MoM5
Computational Patterning and Process Emulation: Linchpins to Enable Continued Scaling through Design Technology Co-optimization for Advanced Nodes
Enabling continued scaling at a pace that meets market demands will require new paradigms to define and evaluate early hardware design guidelines. Increasingly, patterning process implementations will be key factors in defining the boundaries of design spaces available for nodes beyond 10 nm. Self aligned patterning approaches will enable design spaces with significantly different entitlements than direct print patterning strategies due to process control dependencies, complexity, and physical process limitations. Identifying early design guidelines through process simulation and emulation that incorporate a full range of patterning processes required for a given front end of line (FEOL) approach will be key to delivering nodes on time. These processes will undoubtedly include lithography, reactive ion etch, spacer deposition, and wet clean processes. In addition, EUV solutions will require accurate estimates of line width variation, line end pull-back, and new materials challenges that will influence early design decisions. In this talk, we will demonstrate how coupling advanced process simulation with process emulation can be used to evaluate early FEOL design guidelines and establish criteria for equipment and materials vendors. We will also suggest approaches to establishing design entitlement metrics for typical FEOL self aligned patterning processes and EUV direct print approaches that might be used in future gate and fin process modules.