AVS 63rd International Symposium & Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoM

Paper PS-MoM4
Dual Channel Si/SiGe Fin patterning for 10nm Node and Beyond

Monday, November 7, 2016, 9:20 am, Room 104B

Session: Advanced FEOL/Gate Etching
Presenter: Fee Li Lie, IBM Research
Authors: F.L. Lie, IBM Research
E. Miller, IBM Research
P. Xu, IBM Research
S. Sieg, IBM Research
M. Sankarapandian, IBM Research
S. Schmitz, Lam Research Corporation
P. Friddle, Lam Research Corporation
G. Karve, IBM Research
J. Strane, IBM Research
K.Y. Lim, GLOBALFOUNDRIES, Inc.
K. Akarvardar, GLOBALFOUNDRIES, Inc.
M.G. Sung, GLOBALFOUNDRIES, Inc.
S. Kanakabasapathy, IBM Research
Correspondent: Click to Email
As geometric scaling of silicon CMOS technology reaches its limits, continued device performance enhancement requires innovative approaches such as alternative channel materials. Owing to its relatively high hole mobility, much attention has been given to SiGe as a candidate for PFET channel material. The introduction of Ge in the material system affects the vertical and lateral etch behavior of the system depending on the Ge%. Typical balancing act of sidewall passivation and etch to yield vertical and on-target critical dimension (CD) fins now needs to be done on both Si and SiGe simultaneously. Furthermore, subsequent dry/wet clean processes, which generally does not impact Si fins, also interacts with SiGe fin and affects the final fin profile and CD. In this paper, we will present key challenges and approaches pertaining to etching dual channel Si/SiGe fin and subsequent dry/wet clean processes.