AVS 63rd International Symposium & Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoM

Paper PS-MoM10
Hybrid Fin reveal for tight Fin Pitch Technologies

Monday, November 7, 2016, 11:20 am, Room 104B

Session: Advanced FEOL/Gate Etching
Presenter: Peng Xu, IBM Research Division
Authors: P. Xu, IBM Research Division
P. Wang, Lam Research Corporation
Z.X. Bi, IBM Semiconductor Technology Research
T. Devarajan, IBM Research Division
B. Nagabhirava, Lam Research Corporation
A. Basavalingappa, Lam Research Corporation
F.L. Lie, IBM Research Division
J. Strane, IBM Research Division
M. Sankarapandian, IBM Research Division
S. Mehta, IBM Research Division
R. Conti, IBM Research Division
M. Goss, LAM Research Corporation
D. Canaperi, IBM Research Division
D. Guo, IBM Research Division
S. Kanakasabapathy, IBM Research Division
Correspondent: Click to Email

FinFET based CMOS technologies continue scaling down in Fin Pitch1-3. Self-aligned double patterning (SADP) and Self-aligned quadruple patterning (SAQP) have been used to form tight Fin pitch structure. Device requirements and layout constraints can result in the need to cut different numbers of fins, which form variable spaces between fins, but a consistent Fin height must be maintained. In addition to the space variability, gap fill oxide density variations are observed depending on local feature density. A key process for defining the height of the active fin for Bulk Substrates is the Fin reveal process

Such space and film density variations between Fins introduce significant challenges for the Fin reveal process, especially in the sub 40nm Fin pitch range. In this paper, we show initial results from a hybrid Fin reveal process, that combines anisotropic etching with reactive clean techniques. We show the ability to maintain fin reveal depth uniform across feature densities and quality.

1.Chang et al., "Extremely scaled silicon nano-CMOS devices," in Proceedings of the IEEE, vol. 91, no. 11, pp. 1860-1873, Nov 2003.
2.K. I. Seo et al., "A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI," VLSI Technology (VLSI-Technology): Digest of Technical Papers, 2014 Symposium on, Honolulu, HI, 2014, pp. 1-2.
Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, and Yu Cao. 2012. Exploring sub-20nm FinFET design with predictive technology models. In Proceedings of the 49th Annual Design Automation Conference (DAC '12). ACM, New York, NY, USA, 283-288.