| AVS 63rd International Symposium & Exhibition | |
| Plasma Science and Technology | Monday Sessions |
| Session PS-MoA |
| Session: | Advanced BEOL/Interconnect Etching |
| Presenter: | Mark Kiehlbauch, Micron Technology |
| Correspondent: | Click to Email |
Interconnect challenges in memory are driven by scaling, novel architectures, and novel memories.
As NAND and DRAM scale, the pitch of the lower levels of metal routing shrink concurrently. With the delay in EUV lithography, 193 immersion together with complex pitch multiplication and multipatterning schemes have been implemented. These have etch challenges with regard to LWR, selectivity, and feature scale CDU.
The implementation of so-called More than Moore in memory is primarily TSV and 3D packaging to deliver multichip memory packages with extremely high bandwidth and also memory plus logic packages. Over the past several years, the integration of these technologies into high performance and cost effective packages has driven a continuous refinement of etch requirements.
Finally, new memory technologies have resulted in aggressive scaling of interconnects with unique profile and CDU requirements.
In each case, the process, hardware, and integration approaches to address these problems will be discussed.