Paper PS-MoA2
An Investigation into the Mechanism of High Selectivity SiO_x and SiN_x Dielectric Etching

Monday, November 7, 2016, 2:00 pm, Room 104B

As the semiconductor industry drives critical dimensions smaller for 7nm technology node and beyond, the challenges to dielectric etch for logic and memory chip manufacturing become ever greater. The established method of high performance dielectric etching is to employ a plasma process using a fluorocarbon (FC) gas that provides material-dependent selective deposition and sidewall passivation as the etch proceeds. Depending on the FC gas chemistry, SiO­_x will etch selectively over SiN­_x or vice versa. We investigate dielectric etch process parameters that influence dielectric material selectivity (SiO­_x/SiN­_x or SiN­_x /SiO­_x) and pattern fidelity, including gas type and wafer temperature. We also study the possibility of improving selectivity by separating the FC deposition and etching steps (i.e. atomic layer etching).