AVS 63rd International Symposium & Exhibition
    Plasma Science and Technology Monday Sessions
       Session PS-MoA

Paper PS-MoA10
The Impact of Gate Overlap on Self-Aligned Contact (SAC) Etching

Monday, November 7, 2016, 4:40 pm, Room 104B

Session: Advanced BEOL/Interconnect Etching
Presenter: Jeffrey Shearer, IBM Research Division, Albany
Authors: J.C. Shearer, IBM Research Division, Albany
A.P. Labonte, GLOBALFOUNDRIES
J.M. Lucas, Tokyo Electron - TTCA
A. Metz, Tokyo Electron - TTCA
J.C. Arnold, IBM Research Division, Albany
Correspondent: Click to Email
In order to maintain aggressive scaling trends, gate and contact pitches have been reduced to a level requiring robust contact-to-gate self-alignment in order to mitigate gate-to-contact short concerns. Developing novel reactive ion etch (RIE) chemistries to achieve the necessary etch selectivity to the gate cap is one of the more critical challenges in integrated circuit (IC) process development and manufacturing. Further complicating the process space is that selectivity is impacted by the contact-to-gate overlap. This overlap can be intentionally modulated by pitch demands, mask design, and contact critical dimension (CD) or unintentionally modulated by contact-to-gate overlay shifts. Data will show a substantial difference in selectivity between one-sided (borderless) and two-sided (“true SAC”) contact-to-gate overlaps. As both situations could exist on-wafer, it is increasingly difficult to develop robust processes that can accommodate a variety of different contact designs at the same time. The data will show how process optimization can minimize some of the challenges in developing a robust process space and will explore the parameter space that can maximize the SAC selectivity process window across multiple overlap regimes. Lastly, it will be shown how overetch impacts the selectivity of the gate cap in terms of the contact-to-gate overlap. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.