Paper EM1-WeM11
High-k Dielectric/InGaAs MOSCAPs with EOTs 0.7 nm and Low Interface Trap Densities

Wednesday, October 30, 2013, 11:20 am, Room 101 B

A major challenge for future high performance metal-oxide-semiconductor field effect transistors (MOSFETs) is the development of high-k dielectrics, such as Al₂O₃ and HfO₂. A large density of interface traps (Dit) is typical for highly scaled dielectrics on III-V semiconductor channels and causes inefficient Fermi level response or even Fermi level pinning. In this presentation, we show a novel surface preparation method using alternating cycles of nitrogen plasma and trimethyaluminum (TMA) pulse on III-V surface before atomic layer deposition (ALD) of HfO₂ gate stack. We show that nitrogen plasma cleaned stacks exhibit much reduced frequency dispersion in depletion that is due to midgap D_it even for highly scaled stacks. This technique allows for highly scaled HfO₂/n-In_0.53Ga_0.47As gate stacks with equivalent oxide thicknesses (EOTs) of less than 0.7 nm and midgap D_it values less than 4x10¹² cm^-2 eV^-1. Interface trap densities are characterized by capacitance-based and conductance methods. High-quality HfO₂ MOSCAPs exhibit accumulation capacitance densities above 2.5 µF/cm². We report on the interfacial layer thickness, analyze the interface chemistry and bonding, and discuss the reason for the improve performance of nitrogen plasma cleaned gate stacks.